In semiconductor technologies, critical-dimension (CD) variations can be induced by optical interference and other effects. As a result, a mask error factor (MEF) will become too high and unacceptable for smaller feature sizes in sub-wavelength patterning, especially for contact holes. Various techniques have been implemented to improve MEF, including using a phase shift mask (PSM), such as chromeless phase shift mask, to define circuit patterns. In a chromeless phase shift mask, a circuit feature is defined in a transparent mask with phase shift between adjacent transparent regions such that destructive interference generates a dark feature when imaged to a semiconductor substrate. However, a conventional chromeless phase shift mask provides limited freedom to improve imaging quality and other issues, such as etch processing window relative to an expected phase shift. Furthermore, the conventional chromeless phase shift mask has limited protection to the transparent substrate from damage during a process making or using the mask. Therefore, what are needed are a chromeless phase shift mask structure and a method making and using the same to address the above issues.